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<title>RCPSS—Compute Reciprocal of Scalar Single-Precision Floating-Point Values </title></head>
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<h1>RCPSS—Compute Reciprocal of Scalar Single-Precision Floating-Point Values</h1>
<table>
<tr>
<th>Opcode*/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>F3 0F 53 /<em>r</em></p>
<p>RCPSS <em>xmm1</em>, xmm2/m32</p></td>
<td>RM</td>
<td>V/V</td>
<td>SSE</td>
<td>Computes the approximate reciprocal of the scalar single-precision floating-point value in <em>xmm2/m32</em> and stores the result in <em>xmm1</em>.</td></tr>
<tr>
<td>
<p>VEX.NDS.LIG.F3.0F.WIG 53 /r</p>
<p>VRCPSS <em>xmm1, xmm2, xmm3/m32</em></p></td>
<td>RVM</td>
<td>V/V</td>
<td>AVX</td>
<td>Computes the approximate reciprocal of the scalar single-precision floating-point value in <em>xmm3/m32</em> and stores the result in <em>xmm1</em>. Also, upper single precision floating-point values (bits[127:32]) from <em>xmm2</em> are copied to <em>xmm1</em>[127:32].</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr>
<tr>
<td>RVM</td>
<td>ModRM:reg (w)</td>
<td>VEX.vvvv (r)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>Computes of an approximate reciprocal of the low single-precision floating-point value in the source operand (second operand) and stores the single-precision floating-point result in the destination operand. The source operand can be an XMM register or a 32-bit memory location. The destination operand is an XMM register. The three high-order doublewords of the destination operand remain unchanged. See Figure 10-6 in the <em>Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1</em>, for an illustration of a scalar single-precision floating-point operation.</p>
<p>The relative error for this approximation is:</p>
<p>|Relative Error| ≤ 1.5 ∗ 2<sup>−12</sup></p>
<p>The RCPSS instruction is not affected by the rounding control bits in the MXCSR register. When a source value is a 0.0, an ∞ of the sign of the source value is returned. A denormal source value is treated as a 0.0 (of the same sign). Tiny results (see Section 4.9.1.5, “Numeric Underflow Exception (#U)” in <em>Intel® 64 and IA-32 Architectures Soft-ware Developer’s Manual, Volume 1</em>) are always flushed to 0.0, with the sign of the operand. (Input values greater than or equal to |1.11111111110100000000000B∗2<sup>125</sup>| are guaranteed to not produce tiny results; input values less than or equal to |1.00000000000110000000001B*2<sup>126</sup>| are guaranteed to produce tiny results, which are in turn flushed to 0.0; and input values in between this range may or may not produce tiny results, depending on the implementation.) When a source value is an SNaN or QNaN, the SNaN is converted to a QNaN or the source QNaN is returned.</p>
<p>In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).</p>
<p>128-bit Legacy SSE version: The first source operand and the destination operand are the same. Bits (VLMAX-1:32) of the corresponding YMM destination register remain unchanged.</p>
<p>VEX.128 encoded version: Bits (VLMAX-1:128) of the destination YMM register are zeroed.</p>
<h2>Operation</h2>
<p><strong>RCPSS (128-bit Legacy SSE version)</strong></p>
<pre>DEST[31:0] (cid:197) APPROXIMATE(1/SRC[31:0])
DEST[VLMAX-1:32] (Unmodified)</pre>
<p><strong>VRCPSS (VEX.128 encoded version)</strong></p>
<pre>DEST[31:0] (cid:197) APPROXIMATE(1/SRC2[31:0])
DEST[127:32] (cid:197) SRC1[127:32]
DEST[VLMAX-1:128] (cid:197) 0</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>RCPSS:</p>
<p>__m128 _mm_rcp_ss(__m128 a)</p>
<h2>SIMD Floating-Point Exceptions</h2>
<p>None.</p>
<h2>Other Exceptions</h2>
<p>See Exceptions Type 5.</p></body></html>